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Freescale Semiconductor, Inc.
Technical Data
MC44BC373/374 Rev. 3.5, 7/2003 MC44BC373/374 Multi-Standard or PAL/ NTSC Modulator with integrated antenna booster/splitter ICs
MC44BC373/374
TSSOP 24 Package
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Ordering Information
Device MC44BC373DTB,R2 MC44BC374DTB,R2 Temp Range -10oC to +80oC Package TSSOP24
NOTE: For tape and reel, add R2 suffix.
Contents
Features . . . . . . . . . . . . . 2 Device Overview . . . . . . 3 Maximum Ratings . . . . . 5 Electrostatic Discharge 5 Electrical Characteristics 5 6 I2C Bit Mapping . . . . . . . 6 7 I2C Programming . . . . . 7 8 Modulator High Frequency Characteristics 9 9 Video Characteristics . 10 10 Audio Characteristics . 11 11 Antenna Booster/Splitter Characteristics 12 12 Modulator Operation . 14 13 High-Speed I2C Compatible Bus 18 14 Application and Case Diagrams 21 1 2 3 4 5
These modulator ICs are for use in VCRs, games, set-top boxes, and similar devices. Figure 1 shows the pin connections.
SCL SDA 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 GNDD VCCD PLLFLT TVOVCC TVOUT GND GND VCRTU VCRVCC VCCA VIDEO VCCI
LOP XTAL
GND ANT1 ANT2 GND PREEM AUDIO SPLFLT AUXIN
Figure 1. MC44BC373/374 Pin Connections
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. (c) Motorola, Inc., 2003. All rights reserved.
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Features
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1 Features
MC44BC373: Multi-Standard PAL/SECAM/NTSC with integrated booster splitter MC44BC374: PAL/NTSC with integrated booster splitter The channel is set by an on-chip high-speed I2C compatible bus receiver. A Phase-Locked Loop (PLL) tunes the modulator over the full UHF range. The modulator incorporates a sound subcarrier oscillator and uses a second PLL to derive 4.5, 5.5, 6.0, and 6.5MHz subcarrier frequencies. These frequencies are selected using the bus. The picture-to-sound ratio is adjusted using the bus. In addition, an on-chip video test pattern generator can be switched ON using a 1kHz audio test signal. Along with the modulator functions, an Antenna Booster/Splitter function is included. These modulator versions are completely pin-to-pin and software compatible and all versions have the following features. * * * * * * * * * * * * * * * * * No external varicaps diodes/inductors or tuned components Channel 21-69 UHF operation VHF range possible by internal dividers (30MHz to 450MHz) Integrated on-chip programmable UHF oscillator Extremely low external component count High-speed read and write I2C-bus compatible (800kHz) Fixed video modulation depth (80% in PAL and 90% in SECAM) Peak White Clip disabled using the bus Programmable picture/sound carrier ratio (12dB and 16dB) Integrated on-chip programmable sound subcarrier oscillator (4.5MHz to 6.5MHz)--No external varicaps On-chip video test pattern generator with sound test signal (1kHz) Low-power programmable modulator standby mode (booster active) Transient output inhibit during PLL Lock-up at Power-ON Logical Output Port controlled by bus Integrated Antenna Booster/Splitter (40MHz to 860MHz) Custom masked versions with unique start-up settings possible (no I2C bus programming required) Extremely robust ESD protection, minimum 4kV, typical 6kV
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2
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Freescale Semiconductor, Inc.
Device Overview
2 Device Overview
Figure 2 shows a simplified block diagram of the MC44BC373/4 device. The MC44BC373/374 device contains four main sections: 1. A high-speed I2C-compatible bus section. 2. A PLL section -- Synthesizes the UHF/VHF output channel frequency (from an integrated UHF oscillator, divided for VHF output). 3. A modulator section -- Accepts audio and video inputs and then uses those inputs to modulate the UHF/VHF carrier. 4. An Antenna Booster/Splitter -- Amplifies and splits the antenna signal into two signals: a) The modulated signal is added to the amplified antenna signal on the TVOUT pin. a)
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The following items are programmable using the high-speed I2C compatible bus: * * * Channel frequency Sound frequency Sound/picture carrier ratio
An on-chip video test pattern generator with an audio test signal is included. The MC44BC373 operates as a multi-standard modulator and can handle the following systems using the same external circuit components: * * * * * * * * B/G I D/K H L M/N Antenna Booster/Splitter UHF tank circuit and certain filtering
The high frequency BiCMOS technology permits integration of the following functions:
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3
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4
LOP 3 BST SECTION I C BUS L/BG 75 Sound PFD Video Modulator 31.25 kHz
2
VIDEO 14 MODULATOR SECTION
SPLLFLT 11
Device Overview
GND 19 Clamp
Peak White
GND 18
10 AUDIO 9 PREEM
TVOVCC 21 L/BG LPF 75 Prog Divider LPF ALC LPF Sound Oscillator and FM Modulator
TVOUT 20
Audio Amplifier
VCCI 13 16 I2C BUS
VCRTU 17 5 4dB 8 6 7 BUS SECTION VHF Dividers UHF OSC Prescaler/8 I2C BUS 23 VCCD 24 GNDD Sound Modulator AM FM
15 VCCA L/BG AM Modulator 12 AUX IN VCO and PLL SECTION
I2C BUS
GND
GND
ANT2
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Figure 2. Simplified Block Diagram--MC44BC373/374
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ANT1
PLL
I2C BUS
SCL 1
SDA 2
High-Speed I2C Bus Receiver
Prog Divider
Phase Comp
Ref Divider /128 31.25kHz 22 PLLFLT
4MHz XCO
4 XTAL
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Freescale Semiconductor, Inc.
Maximum Ratings
3 Maximum Ratings
Sym Vcc1 Tamin Tamax Supply Voltage Minimum Operating Ambient Temperature Maximum Operating Ambient Temperature Parameter Value Unit 6 -10 75 -65 150 V
o
C
oC o o
Tstgmin Minimum Storage Temperature Tstgmax Maximum Storage Temperature
C C
This device contains protection circuitry to guard against damage due to high static voltage or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, input and output voltages should be constrained to the ranges indicated in the Recommended Operating Conditions.
Maximum ratings are those values beyond which damage to the device may occur. For functional operation, voltage should be restricted to the Recommended Operating Condition.
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4 Electrostatic Discharge
Sym ESD Parameter HBM (Human Body Model)--MIL-STD-883C, Method 3015-7 Min 4000 Typ 6000 Unit V
5 Electrical Characteristics
* * * * A = 100% Tested B = 100% Correlation tested C = Characterized on samples D = Design parameter
5.1 Specification Conditions
Unless otherwise stated: Vcc = 5.0 V, Ambient Temperature = 25o C, Video Input 1Vp-p, 10-step grayscale. RF inputs/outputs into 75Ohm load. SPECIFICATIONS ONLY VALID FOR ENVELOPE DEMODULATION.
Parameter Operating supply voltage range Total supply current Total standby mode supply current Test pattern sync pulse width Sound comparator charge pump current During locking When locked RF comparator charge pump current Crystal oscillator stability-negative resistance Logic Output Port Saturation voltage at I=2mA Leakage current Min 4.5 65 26 3 7 0.7 60 1 -- -- Typ 5.0 75 34 4.7 10 1 100 -- 160 -- Max 5.5 88 40 6.5 12 1.5 150 -- 300 1 mA S A A A K mV A Unit V All sections active OSC, SO, ATT=1 Bus Section active Notes Type B A A B A A A D A A
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5
I2C Bit Mapping
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6 I2C Bit Mapping
WRITE MODE CA-CHIP ADDRESS C1-High Order Bits C0-Low Order Bits FM-High Order Bits FL-Low Order Bits READ MODE CHIP ADDRESS R-Status Byte Bit Name Bit 7 1 1 PWC 0 N5 Bit 7 1 -- Bit 6 1 AUX OSC TPEN N4 Bit 6 1 -- Bit 5 0 SO ATT N11 N3 Bit 5 0 -- Bit 4 0 LOP SFD1 N10 N2 Bit 4 0 -- Description Peak White Clip enable/disable. UHF oscillator ON/OFF. Modulator output attenuated-sound and video modulators ON/OFF. Sound subcarrier frequency control bits. Test mode bit--bus format compatible with MC44353. Auxiliary sound input enable/disable. Sound Oscillator ON/OFF. Logic Output Port. Picture-to-Sound carrier ratio. System L enable--selects AM sound and positive video modulation (MC44BC373/ only). Test pattern enable--picture and sound. Test mode bits--All bits are 0 for normal operation (see Test Mode tables, page 7 & page 8). UHF frequency programming bits, in steps of 250kHz. RF oscillator out-of-frequency range information. RF oscillator operating range information. Bit 3 1 PS SFD0 N9 N1 Bit 3 1 -- Bit 2 0 X3 TB1 N8 N0 Bit 2 0 Y2 Bit 1 1 X2 X5 N7 X1 Bit 1 1 Y1 Bit 0 0 SYSL X4 N6 X0 Bit 0 1 OOR ACK ACK ACK ACK ACK ACK ACK ACK --
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PWC OSC ATT SFD0, 1 TB1 AUX SO LOP PS SYSL TPEN X5...X0 N0...N11 OOR Y1, Y2
6
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I2C Programming
7 I2C Programming
Sound
SFD1 0 0 1 1 PS 0 1 SFD0 0 1 0 1 Sound Subcarrier Freq (MHz) 4.5 5.5 6.0 6.5 Picture-to-Sound Ratio (dB) 12 16 Sound Oscillator Sound oscillator ON (normal mode). Sound oscillation disabled (oscillator and PLL section bias turned OFF). Auxiliary Audio Input AUX input disabled (normal mode). AUX input enabled. 1 1 1 ATT 0 1
UHF
OSC 0 1 UHF Oscillator Normal operation. UHF oscillator disabled (oscillator and PLL sections bias turned OFF). Modulator Output Attenuation Normal operation. Modulator output attenuation (sound and video modulators sections bias turned OFF).
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SO 0 1 AUX 0 1
Standby Mode
OSC SO ATT Combination of 3-bits Modulator standby mode (sound and UHF oscillator, sound and video modulator section bias turned OFF, and I2C bus section standby mode)--BST is active.
MC44353/4/5 Compatibility
TB1 Description Normal mode (fully programmable). Limited programmability and compatibility with MC44353.
Video
SYSL 0 1 PWC 0 1 TPEN 0 System L and B/G Selection MC44BC373 only System B/G enabled, System L disabled (FM sound and negative video modulation). System L enabled, System B/G disabled (AM sound and positive video modulation). Peak White Clip Peak White Clip ON (System B/G). Peak White Clip OFF (System L). Test Pattern Signal Test pattern signal OFF (normal operation). 0 1
Logic Output Port
LOP 0 1 Description Pin 3 is low voltage. Pin 3 is high impedance.
WRITE MODE: Test Mode 1 and VHF Range
X2 0 0 0 0 1 1 1 1 X1 0 0 1 1 0 0 1 1 X0 0 1 0 1 0 1 0 1 State 1.a 1.b 1.c 1.d 1.e 1.f 1.g 1.h Normal operation. RF frequency divided for low frequency testing or VHF range: RF/2 RF/4 RF/8 RF/16 DC drive applied to modulators: non-inverted video at TVOUT. DC drive applied to modulators: inverted video at TVOUT. Transient output inhibit disabled. Description
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7
I2C Programming
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WRITE MODE: Test Mode 2
X5 0 0 0 0 1 X4 0 0 1 1 0 X3 0 1 0 1 0 State 2.a 2.b 2.c 2.d 2.e Normal operation. Test pattern generator DC verification (Test pattern DC test mode available). Programmable divider test (UHF programmable divider on PLLFILT pin and sound programmable divider on SPLLFIL pin). Reference divider test (UHF reference divider on PLLFILT pin). UHF phase comparator, upper source on PLLFILT pin. Sound phase comparator 10A upper source on SPLLFIL (only valid during Transient Output Inhibit). UHF phase comparator, lower source on PLLFILT pin. Sound phase comparator 10A lower source on SPLLFIL (only valid during Transient Output Inhibit). Sound phase comparator 1A upper source on SPLLFIL (not valid during Transient Output Inhibit). Sound phase comparator 1A lower source on SPLLFIL (not valid during Transient Output Inhibit). Description
1
0
1
2.f
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1 1
1 1
0 1
2.g 2.h
READ MODE
OOR 0 1 Y1 0 1 Y2 0 1 High VCO is active. Low VCO is active. Normal operation, VCO in range. VCO out-of-range. Description VCO out-of-range, frequency too low, only valid if OOR=1. VCO out-of-range, frequency too high, only valid if OOR=1. Description Description
8
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Freescale Semiconductor, Inc. Modulator High Frequency Characteristics
8 Modulator High Frequency Characteristics
Unless otherwise stated: Vcc=5.0 V, Ambient Temperature =25o C, Video Input 1Vp-p, 10-step grayscale. RF inputs/outputs into 75Ohm load. SPECIFICATIONS VALID ONLY FOR ENVELOPE DEMODULATION.
Parameter TVOUT output level UHF oscillator frequency VHF range TVOUT output attenuation Test Conditions Output signal from modulator section. See Figure 3. -- From UHF oscillator internally divided. During transient output inhibit, or when ATT bit is set to 1. See Figure 3. Using red EBU bar. Using red EBU bar. 2nd harmonic: CH21 3rd harmonic: CH21 Other channels: See Figure 3. See NOTE 1. 1/2Fo-1/4Fo-3/2Fo-3/4Fo From 40MHz to 1GHz. No video sound modulation. Min 73 460 45 50 -- -65 -65 30 20 Typ 74.5 -- -- 60 -63 -- -- 35 26 Max 77 880 460 -- -58 -- -- -- -- Unit dBV MHz MHz dBc dBc dBc dBc Type B A B B C C C
Sound subcarrier harmonics (Fp+nFs) Reference picture carrier.
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Second harmonic of chroma subcarrier Chroma/Sound intermodulation: Fp + (Fsnd - Fchr) Fo (picture carrier) harmonics
dBc
C
Out band (picture carrier) spurious In band spurious (Fo 5MHz)
-- --
0 --
10 60
dBV dBc
C C
NOTE 1: Picture carrier harmonics are highly dependant on printed circuit board layout and decoupling capacitors.
2Fo Har m onics 40 35
45 40 35 3Fo Har m onics
Typical
dBc
Typical
dBc
30 25 20 15 471
30 25 20
Minimum specification
521 571 621 671 721 771 Fre que ncy (M hz)
TV Output Le ve l
821 871
15 471
Minimum specification
521 571 621 671 721 771 821 871
Fre que ncy (M hz)
T V O u t p u t A t t e n u at io n 75 70 65
78 77 76
Maximum specification
dBuV
75 74 73 72 471
dBc
Typical
60 55 50
Typical
Minimum specification
521 571 621 671 721 771 821 Fre que ncy (M hz) 871
45 47 1 52 1 5 71 62 1 67 1 7 21 7 71 8 2 1 8 71 Fr e q u e n c y ( M h z )
Minimum specification
Figure 3. Typical Performance--Modulator High Frequency
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9
Video Characteristics
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9 Video Characteristics
Unless otherwise stated: Vcc = 5.0 V, Ambient Temperature = 25 o C, Video Input 1Vp-p, 10-step grayscale. RF inputs/outputs into 75Ohm load. SPECIFICATIONS VALID ONLY FOR ENVELOPE DEMODULATION.
Parameter Video bandwidth Video input level Video input current Video input impedance Peak White Clip Video S/N Differential Phase Differential Gain Luma/Sync ratio PAL video modulation depth SECAM video modulation depth Test Conditions Reference 0dB at 100kHz, measured at 5MHz. 75Ohm load. -- -- PWC bit set to 1, see PWC section. See Figure 4. See Figure 4. On line CCIR 310, worst of first 4 out of 5 steps. See Figure 4. Input ratio 7.0 : 3.0 -- --
V ide o Signal to Nois e 58 56
Min -1.5 -- -- 500 110 50 -5 -5 6.8/3.2 75 88
Typ -0.8 -- 0.2 -- 114 53 -- -- -- 81 93
Max -- 1.5 1 -- 118 -- 5 5 7.2/2.8 88 99
Unit dB Vcvbs A K % dB deg % -- % %
Type C D A A A C C C B B B
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Typical
54
dB
52 50 48 471 521 571 621 671 721 771 Fre que ncy (M hz)
Minimum specification
821 871
PA L V id e o M o d u latio n De p th 90 88 86 84
%
SEC A M V id e o M o d u latio n De p th 100 98
Maximum specification Typical
%
96 94 92 90 88
Maximum specification Typical
82 80 78 76
74 Minimum specification 471 521 571 621 671 721 771 821 871 Fr e q u e n cy (M h z )
86 471 521 571 621 671 721 771 821 871 Fr e q u e n cy (M h z )
Minimum specification
Figure 4. Typical Performance--Video
10
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Audio Characteristics
10 Audio Characteristics
Unless otherwise stated: Vcc = 5.0 V, Ambient Temperature = 25 o C, Video Input 1Vp-p, 10-step grayscale. RF inputs/outputs into 75Ohm load. SPECIFICATIONS VALID ONLY FOR ENVELOPE DEMODULATION.
Parameter Picture-to-Sound ratio Test Conditions PS bit set to 0. PS bit set to 1. Min 13 9 Typ 16 12 Max 19 15 Unit dB Type B
Using specific pre-emphasis circuit, audio input level=205mVrms-audio frequency=1kHz AM modulation: SECAM Fs=6.5MHz Audio modulation depth FM modulation: Fs=5.5, 6 or 6.5MHz 100% modulation=50kHz FM deviation FM modulation: NTSC Fs=4.5MHz 100% modulation=25kHz FM deviation Audio input resistance Audio Frequency response -- Reference 0dB at 1kHz, using specified pre-emphasis circuit, measure from 50Hz to 15kHz. At 1kHz, 100% modulation (50kHz). No video. At 1kHz, 100% modulation. No video. Video input EBU color bar 75%. Weighting filter CCIR 468-2. Reference 1kHz, 85% modulation. Video input EBU color bar 75%. Audio BW from 40Hz to 15kHz. Weighting filter CCIR 468-2.
Audio Signal to Noise 58 56 54 dB 52 50 48 46 471 521 571 621 671 721 771 821 871 Frequency (Mhz)
65 65 65 45
80 80 80 53
95 95 95 61
% % % K
B B B A
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-2.5 -- -- 48
-- 0.4 1.5 53
+2 2 2.5 --
dB % % dB
C C D C
Audio Distortion FM (THD only) Audio Distortion AM (THD only) Audio S/N with Sync Buzz FM
Audio S/N with Sync Buzz AM
45
50
--
dB
D
Typical
Minimum specification
Figure 5. Typical performance--Audio
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11
Antenna Booster/Splitter Characteristics
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11 Antenna Booster /Splitter Characteristics
Unless otherwise stated: Vcc = 5.0 V, Ambient Temperature = 25 o C, RF inputs / outputs into 75 Ohm load. All specifications use a BALUN at ANT1 & 2 inputs, assuming 0.8dB losses MAX from 40MHz to 860MHz.
Parameter Frequency range Gain Gain flatness Noise figure Noise figure -- ANT1, 2 to VCRTU. ANT1, 2 to TVOUT. 40 to 860MHz. ANT1, 2 to VCRTU and TVOUT. Modulator in standby mode. ANT1, 2 to VCRTU and TVOUT. Modulator in normal mode (ON). All pins, BST bias ON. At TVout and VCRTU pins, BST bias OFF. At TVin pins, BST bias OFF. Intermodulation (IMD) Isolations Input level=90dBuV. See IMD measurement section. F1+F2 IMD 2F1-F2, 2F2+F1, F1-F2 IMD From TVOUT or VCR to ANT1, 2 TVOUT/VCRTU Test Conditions Min 40 -- -1.5 5.5 6.5 -- -- -- -- 48 30 7.5 8.5 1.5 2.5 55 60 60 45 Typ -- 4 4 Max 860 -- +1.5 9.5 10.5 2.5 3 47 50 -- -- Unit MHz dB dB dB dB dB -- -- dBc dBc dBc dBc Type C B B C C C B B C C C C
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VSWR
11.1 Typical Performance--Gain and Isolation
Gain ANT1,2 to VCRTU and TVOUT 7 6 5
dB
Maximum specification
4 3 2 1 0 150 300 450 600 750 900
Fre que ncy (M hz)
Typical Minimum specification
TV OUT V CRTU
Is ola tion Output to Input
-30 -40 -50
dBc
Is o latio n Ou tp u t to Ou tp u t -10 -20 -30
dBc
Minimum specification
Minimum specification
-60 -70 -80 -90 0 150 300 450 600 Fr e q u e n cy (M h z ) 750 900
-40 -50
Typical
Typical
-60 -70 0 150 300 450 600 Fr e q u e n cy (M h z ) 750 900
Figure 6. Typical Performance--Gain and Isolation
12
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11.2 Typical Performance--Noise Figure
Noise Figure @ Modulator OFF
11 10 9
Noise Figure @ M odulator ON
12 11 10
Maximum specification
Maximum specification
dB
dB
8 7 6 5 0 150 300 450 600 Fr e que ncy (M hz ) 750 900
9 8 7 6 0 150 300 450 600 Fr e que ncy (M hz ) 750 900
Typical
Typical
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Figure 7. Typical Performance--Noise Figure
11.3 Intermodulation ( IMD ) Measurement
F1
50/75
BALUN TVOUT Pin 20 Pin 17 VCRTU
75/50 Spectrum Analyzer 75/50
F2
MC44BC373/4
90dBuV
IMD (dBc)
2F1-F2
Figure 8. Intermodulation (IMD) Measurement
Intermodulation (IMD) frequencies are all frequency combinations coming from the two input carriers F1 and F2: F2-F1, 2F1-F2, 2F2-F1 and F1+F2, fall in the 40MHz-900MHz range. F1 and F2 input levels are set to 90dBuV at the input of the BALUN. F1 and F2 frequency generator levels (50W internal load) take into account a 50 to 75Ohm load difference (1.8dB), plus losses in the 3dB coupler and the 50 to 75Ohm transformer. Intermodulation measurement is the difference (in dBc) between the F1 or F2 level at the Output (VCRTU or TVOUT) and the frequency combinations level, for the following cases:
F1=50MHz and F2=60MHz F1=300MHz and F2=310MHz F1=600MHz and F2=610MHz F1=100MHz and F2=110MHz F1=400MHz and F2=410MHz F1=700MHz and F2=710MHz F1=200MHz and F2=210MHz F1=500MHz and F2=510MHz F1=800MHz and F2=810MHz
Intermodulation specification is the IMD measurement's worst case.
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F1 F2 2F2-F1
F1+F2
F2-F1
F1 F2
13
Modulator Operation
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12 Modulator Operation
12.1 Power-ON Settings
At power-ON, the MC44BC373 and MC44BC374 configuration is as follows:
WRITE MODE C1--High Order Bits C0--Low Order Bits FM--High Order Bits FL--Low Order Bits Note: Note: Note: Note: Note: Note: 2. Peak White Clip is ON. 3. Sound frequency is 5.5MHz. 4. Sound auxiliary input is disabled. 5. Logic Output Port is low voltage. 6. Picture-to-sound ratio is 12dB. Bit 7 1 0 0 N5 Bit 6 0 0 0 N4 Bit 5 0 0 N11 N3 Bit 4 0 0 N10 N2 Bit 3 0 1 N9 N1 Bit 2 0 0 N8 N0 Bit 1 0 0 N7 0 Bit 0 0 0 N6 0 ACK ACK ACK ACK ACK
1. N0 to N11 are set to have the UHF oscillator on channel 36 (591.25MHz).
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The settings indicated can be customized in the special masked version.
12.2 Power Supply
The five device Vcc pins (13, 15, 16, 21, 23) must be applied at the same time to ensure all internal blocks are correctly biased. All other pins must not be biased before Vcc is applied to the device. The printed circuit board layout of the Vcc supplies must be designed to ensure maximum isolation of the I/P to O/P and also between the two O/Ps.
12.3 Standby Mode
During standby mode, the modulator is switched to low power consumption; the sound oscillator, UHF oscillator, video and sound modulator sections bias are internally turned OFF. The I2C bus and booster sections remain active. The modulator can be programmed in standby mode using a combination of three bits: 1. OSC=1 2. SO=1 3. ATT=1
14
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12.4 Test Bit TB1
Modulator Operation
This test bit allows an initial evaluation of MC44BC373 and MC44BC374 using software developed for MC443535: * * TB1= 0 -- All MC44BC373/374 functions available--normal mode. TB1= 1 -- Limited software compatibility with MC44353; MC44BC373/374 functions not available.
WRITE MODE 1 CA-CHIP ADDRESS C1-High Order Bits C0-Low Order Bits FM-High Order Bits Bit 7 1 1 -- 0 N5 -- TPEN N4 Bit 6 1 Bit 5 0 -- -- N11 N3 Bit 4 0 -- SFD1 N10 N2 Bit 3 1 PS SFD0 N9 N1 Bit 2 0 -- 1 N8 N0 Bit 1 1 -- 0 N7 -- Bit 0 0 SYSL 0 N6 -- ACK ACK ACK ACK ACK ACK
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FL-Low Order Bits Note: Note: 2. All "--" are don't care bits.
1. Case TB1=1, compatible with MC44353
Note: 3. PS bit replaces PSD2 bit in MC44353 bus format: PS = 0 is for picture-to-sound ratio = 12dB, PS = 1 is for picture-to-sound ratio = 16dB Note: 4. SFD1 and SFD0 bits have the same definition for both bus formats (MC44353 and MC44BC373/374) and lets a sound frequency between 4.5MHz, 5MHz, 5.5MHz, and 6.5MHz be selected. Note: 5. SYSL bit has same definition for bus formats MC44353 and MC44BC373/374; either system L or B/G is selectable. Note: 6. All MC44BC373/374 functions are set to their default values.
12.5 System L or B / G Selection
SYSL bit internally switches the following functions: * SYSL = 0; enables B/G system -- Video modulation polarity--Negative -- Video modulation depth--80% Typical (See Video Characteristics on page 10.) -- Sound modulation type--FM * SYSL = 1; enables L system -- Video modulation polarity--Positive -- Video modulation depth--90% Typical (See Video Characteristics on page 10.) -- Sound modulation type--AM
12.6 Transient Output Inhibit
To minimize the risk of interference to other channels while the UHF PLL is acquiring a lock on the desired frequency, the Sound and Video modulators are turned OFF for each of the following two cases: 1. Power-ON from zero (i.e., all Vcc is switched from 0V to 5V). 2. UHF oscillator power-ON from OFF state (i.e., OSC bit is switched from 1 to 0)
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Modulator Operation
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There is a time-out of 263ms until the output is enabled. This allows the UHF PLL settle to its programmed frequency. During the 263ms time-out, the sound PLL current source is set to 10A typical, to speed up the locking time. After the 263ms time-out, the current source is switched to 1 A.
CAUTION:
Use care when selecting loop filter components, to ensure the loop transient does not exceed the specified delay. For test purposes, it is possible to disable the 263ms delay using Test Mode1-State1.h.
12.7 Logic Output Port (LOP)
The LOP pin controls any logic function. The primary applications are to control an external attenuator or an external switch between the antenna input and TV output. When an external switch is controlled, the Booster function is not used.
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The following figure shows a typical attenuator application with PIN diode. The LOP pin switches the PIN attenuator depending on the signal strength of the Antenna Input, thereby reducing the risks of Intermodulation in certain areas. The LOP may also be used as an OFF position bypass switch or for other logic functions in the application.
Vcc
Antenna Input
TV Out
LOP pin
Figure 9. Attenuator Application with PIN Diode
12.8 Video Section--Peak White Clip
The modulator requires the following: * * A composite video input with "negative going" sync pulses A nominal level of 1Vp-p
This signal is AC-coupled to the video input where the sync tip level is clamped. The video signal is then passed to a Peak White Clip (PWC) circuit. The PWC circuit function sets to soft-clip the top of the video waveform, if the "sync tip amplitude" to "peak white clip" goes too high. This method avoids carrier overmodulation by the video. Clipping can be disabled by software.
12.9 Sound Section
The multivibrator oscillator is fully integrated and does not require external components. An internal low pass filter and matched structure provide a very low harmonics level. The sound modulator system consists of an FM modulator incorporating the sound subcarrier oscillator, and an AM modulator. The audio input signal is AC coupled into the amplifier which then drives the two types of modulators. The audio pre-emphasis circuit is a high-pass filter with an external capacitor and an internal resistor (100kOhms). The recommended capacitor value (470pF) is for BG standard. (50S time constant.)
16
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Modulator Operation
The auxiliary audio input adds a sound subcarrier to the main carrier. The input can be a modulated NICAM carrier or a second sound subcarrier for a stereo system. Pin 12 is directly connected to the sound modulator input and the picture-to-sound ratio (P/S Ratio) depends on the auxiliary audio input level. (P/S ratio is 20dB for 35mVrms typical.)
12.10 Test Pattern Generator
A simple test pattern is generated on the IC which can be switched in under bus control to permit a TV receiver to easily tune in to the modulator output. The pattern consists of two white vertical bars on a black background and a 976Hz audio test signal.
TE2
7/10
Freescale Semiconductor, Inc...
3/10
TE1 0 10 20 24 2830 40 44 50 60 64
TIME IN S.
Figure 10. Test Pattern Generator--(Time in Seconds)
12.11 PLL Section
The reference divider is a fixed divide-by-128, resulting in a reference frequency of 31.25KHz with a 4.0MHz crystal. The 31.25KHz reference frequency is used for both UHF and Sound PLLs. The prescaler is a fixed divide by 8 and is permanently engaged. The programmable divider's division ratio is controlled by the state of control bits N0 to N11. The divider ratio N for a desired frequency F (in MHz) is provided by the following formulas:
F 128 N = -- x -------8 4
with:
N = 2048 x N11 + 1024 x N10 + ...... + 4 x N2 + 2 x N1 + N0
12.12 UHF Oscillator--VHF Range
The UHF oscillator is fully integrated and does not require any external components. For low frequency testing or VHF range operation (test mode 1, states 1.b to 1.c), the UHF oscillator can be internally divided by 2, 4, 8, or 16.
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High-Speed I2C Compatible Bus
Freescale Semiconductor, Inc.
13 High-Speed I2C Compatible Bus
13.1 Specification Conditions
Unless otherwise specified, the Vcc1=5.0V and the ambient temperature (TA) =25 o C.
Electrical Characteristics SDA/SCL output current at 0 V SDA/SCL low input level SDA/SCL high input level SDA/SCL input current for input level from 0.4V to 0.3Vcc SDA/SCL input level SDA/SCL capacitance ACK low output level (sinking 3mA) ACK low output level (sinking 15mA) Timing Characteristics Bus clock frequency Bus free time between stop and start Setup time for start condition Hold time for start condition Data setup time Data hold time Setup time for stop condition Hold time for stop condition Acknowledge propagation delay SDA fall time at 3ma sink I and 130pF load SDA fall time at 3ma sink I and 400pF load SDA rise time SCL fall/rise time Pulse width of spikes suppressed by the input filter Min -- -- 3.0 -5 0 -- -- -- Min 0 200 500 500 0 0 500 500 -- -- -- -- -- -- Typ -- -- -- -- -- -- 0,3 -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 10 1.5 -- 5 Vcc+0,3 10 1 1.5 Max 800 -- -- -- -- -- -- -- 300 50 80 300 300 50 Unit A V V A V pF V V Unit kHz ns ns ns ns ns ns ns ns ns ns ns ns ns Type A B B C D C A C Type C C C C C C C C C C C C C C
Freescale Semiconductor, Inc...
13.2 Timing Definitions
Stop Tbuf Start Chip Address
ACK
Start
Stop
SSDA SSCL
... ...
SDA SCL
SDA SCL
Tsu;sto Thd;sta
Tsu;dat
Thd;dat
Tack:low
Tsu;sta
Thd;sto
Figure 11. SSDA/SSCL Timing
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Freescale Semiconductor, Inc. I2C Compatible Bus High-Speed
13.3 Levels Definition
SDA
...
Vcc Vih Vil 0V
dead band
Figure 12. SDA Levels
13.4 High-Speed I2C Compatible Bus Format
SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 44 45
Freescale Semiconductor, Inc...
STA
Chip Address ($CA) ACK
First Data Byte (C1 or FM) ACK
Data ACK
Stop
SDA
Figure 13. SCL and SDA Bus Timing
13.5 I2C Write Mode Format and Bus Receiver
The bus receiver operates the I2C compatible data format. The chip address (I2C bus) is:
1 1 0 0 1 0 1 0 (ACK) = $CA (hex) in write mode
In write mode, each ninth data bit (bits 9, 18, 27, 36, and 45) is an acknowledge bit (ACK) during which the MCU sends a logic 1 and the Modulator circuit answers on the data line by pulling it low. Besides the chip address, the circuit needs two or four data bytes for operation. The following data byte sequences are the permitted incoming information:
Example 1 Example 2 Example 3 Example 4 With: STA = Start condition FM = Frequency information, high order bits C1 = Control information, high order bits STO = Stop condition CA = Chip Address FL = Frequency information, low order bits CO = Control information, low order bits STA STA STA STA CA CA CA CA C1 FM C1 FM C0 FL C0 FL STO STO FM C1 FL C0 STO STO
After the chip address, two or four data bytes may be received. * * If three (3) data bytes are received, the third one is ignored. If five (5) or more data bytes are received, the fifth and following ones are ignored, and the last ACK pulse is sent at the end of the fourth data byte.
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High-Speed I2C Compatible Bus
Freescale Semiconductor, Inc.
The first and third data bytes contain a function bit which lets the IC distinguish between frequency information and control information. If the function bit is a logic 1, the two following bytes contain control information. The first data byte after the chip address may be byte CO or byte FM. The two bytes of frequency information are preceded by a logic 0.
13.6 I2C Read Mode Format
The chip address (I2C) is:
1 1 0 0 1 0 1 1 (ACK) = $CB (hex) in read mode
The incoming information consists of the read mode chip address byte. The device then answers with an ACK followed by one byte containing three bits of status information. No acknowledge is answered by the modulator after this byte.
Freescale Semiconductor, Inc...
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14 Application and Case Diagrams
Proposed BiCMOS Modulator and Booster/Splitter Application
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
SCL
1 2 3 4 5 6 7 8 9
24 23 22
GNDD VCCD
SDA
LOP
4MHz
Cx Note 1 1nF 1nF
LOP
PLLFLT TVOVCC
XTAL GND
21 20
10nF 1nF 1nF 10nF 10nF
Freescale Semiconductor, Inc...
TVOUT
ANTIN O
ANT1 ANT2 GND
19 18 17 16
GND GND
Pre-em
470pF
VCRTU
PREEM AUDIO
VCRVCC
10 11
15
VCCA
SPLLFLT
14 13
VIDEO
100nF 22nF
220nF 1nF 15k
AUXIN
12
VCCI
O Audio
O Auxin
O Vcc
Note 1: Cx value depends on crystal characteristics; Cx = 27pF on Motorola application board. Note 2: Loop filter components must be as close as possible to pins 22 and 23. Figure 14. Proposed BiCMOS Modulator and Booster/Splitter Application
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O Note 2 22nF 47nF O TVOUT 2.2k O VCRTU O Video 100nF 75 21
SDA O
SCL O
Vcc
O
Application and Case Diagrams
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
CASE 940H-02 ISSUE A
Millimeters Dim Min A B C D F G H J J1 K K1 L M 7.70 4.30 -- 0.05 0.51 0.27 0.09 0.09 0.19 0.19 6.25 0
o
Inches Min 0.303 0.169 -- 0.002 0.020 0.011 0.003 0.003 0.007 0.007 0.246 0o Max 0.311 0.176 0.037 0.006 0.028 0.015 0.007 0.005 0.012 0.010 0.256 8o
Max 7.90 4.48 0.95 0.15 0.71 0.37 0.18 0.13 0.30 0.25 6.50 8o
Note: 1. Dimensioning and Tolerancing per ANSI Y14.5M, 1982. Note: 2. Controlling dimension: Millimeters. Note: 3. Dimensions A and B do not include mold flash or protrusions and are measured at the parting line. Mold flash or protrusions shall not exceed 0.15 (0.006) per side. Note: 4. Dimension is the length of terminal for soldering to a substrate. Note: only. 5. Terminal positions are shown for reference
0.65 BSC
0.026 BSC
Note: 6. The lead width dimension does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. Dambar can not be located on the lower radius or the foot. Minimum space between protrusions and adjacent lead to be 0.14 (0.006).
Figure 15. TSSOP24 Package
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Freescale Semiconductor, Inc.
NOTES
Freescale Semiconductor, Inc...
MOTOROLA
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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
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